RFR :7088419 : (L) Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32 and java.util.zip.Adler32
mike.duigou at oracle.com
Thu May 16 16:17:29 UTC 2013
On May 16 2013, at 07:50 , David Chase wrote:
> 4) For CRC32, use the new-ish PCLMULQDQ instruction (64-bit by 64-bit carryless multiply, yielding a 128-bit result) in the style described in Intel's white paper on using this instruction to compute CRCs. All the constants are different because the CRC32 is bit-reversed from the checksums computed in Intel's paper, but the unrolling is the same, and the fill and drain code is also similar. This is by default enabled whenever CLMUL and AVX features are both present, and can be disabled at the command line with -XX:-UseCLMUL (or -XX:-UseAVX).
> There is a companion webrev that puts information about the availability of the PCLMULQDQ in 3-operand form into a hidden property:
I haven't looked at the details for the PCLMULQDQ instruction but a caryless multiply could be of use to some of the crypto primitives as well (GHASH, GMAC and probably others). Perhaps the property could be "sun.hotspot.x64.clmulSupported" or something less specific to the usage.
What's our actual experience with needing switches like -XX:-UseCLMUL or-XX:-UseAVX for other features? Faulty implementations? Feature misreporting? Performance regressions? Virtualization interactions?
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