Short/Character.reverseBytes intrinsics

Hiroshi Yamauchi yamauchi at
Thu Apr 22 15:22:26 PDT 2010

Thanks, Tom. It looks good to me.

> This is Hiroshi's patch for reverseShort and reverseChar intrinsics.
> I've redone the sparc implementation and fixed bugs in the original
> implementation as well.  The existing versions were broken with
> implicit null checking since implicit null checks assume that the
> faulting load is the first instruction in the node but because of the
> way the memory was being handled it wasn't.  The first instruction was
> actually an add so if an implicit null happened the JVM would die.
> The new code restricts these forms to use reg+reg addressing only so
> any address math is handled automatically.  Tested with new test case

I must have overlooked the '+2' offset in the stackSlotI (in

I'm just curious but I'm not sure who emits the add instruction. One
instruction that can be emitted before the load instruction (and that
I can see) is:

949     emit3_simm13( cbuf, Assembler::arith_op, index,
Assembler::or_op3, 0, disp);

emitted by the now-removed emit_form3_mem_reg_asi(). But it's an or,
not an add. There may be some code emission that I don't see.


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