Short/Character.reverseBytes intrinsics

Tom Rodriguez tom.rodriguez at
Thu Apr 22 16:15:43 PDT 2010

Resending because of bounce.

On Apr 22, 2010, at 3:22 PM, Hiroshi Yamauchi wrote:

> Thanks, Tom. It looks good to me.


>> This is Hiroshi's patch for reverseShort and reverseChar intrinsics.
>> I've redone the sparc implementation and fixed bugs in the original
>> implementation as well.  The existing versions were broken with
>> implicit null checking since implicit null checks assume that the
>> faulting load is the first instruction in the node but because of the
>> way the memory was being handled it wasn't.  The first instruction was
>> actually an add so if an implicit null happened the JVM would die.
>> The new code restricts these forms to use reg+reg addressing only so
>> any address math is handled automatically.  Tested with new test case
> I must have overlooked the '+2' offset in the stackSlotI (in
> bytes_reverse_unsigned_short/bytes_reverse_short.)

It showed up in testing of course.  I didn't notice it before that.

> I'm just curious but I'm not sure who emits the add instruction. One
> instruction that can be emitted before the load instruction (and that
> I can see) is:
> 949     emit3_simm13( cbuf, Assembler::arith_op, index,
> Assembler::or_op3, 0, disp);
> emitted by the now-removed emit_form3_mem_reg_asi(). But it's an or,
> not an add. There may be some code emission that I don't see.

That code was doing or g0, simm13, o7.  On sparc both add and or can be used for the constant formation idiom though you decompose the constant differently when sethi is involved since it does 22 bits and the others do 13 so they overlap.  sethi hi22, r or r, simm13, r always works but an add has to operate on the low 10 bits.


> Hiroshi

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