Request for reviews (S): 6990015: Incorrect Icache line size is used for 64 bit x86
vladimir.kozlov at oracle.com
Tue Jun 28 12:23:07 PDT 2011
Paul Hohensee wrote:
> Your comment in the CR is correct: 32 bytes is used because that's the L1
> icache line size on early AMD chips, including, if I recall correctly (and I
> might be wrong), Opterons. So we might trigger the guarantee in some
> obscure cases, but it'll be obvious what the problem is.
AMD says there were never x64 cpus with 32 bytes cache line. Yes, before x64
there were AMD cpus which had 32 bytes cache line.
> You might want to change the second guarantee to*
> guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size * 8 ==
> ICache::line_size, "clflush size is not supported");
I don't think it is correct. clflush_size defines what clflash instruction
flashes which could be different from Icache line size. For example, on sparc it
> On 6/28/11 1:49 PM, Vladimir Kozlov wrote:
>> This is for 7u2.
>> Fixed 6990015: Incorrect Icache line size is used for 64 bit x86
>> Until 7059226 is fixed we can't use information from cpuid to
>> determine the cache flashing size since flush_icache stub have to be
>> generated before cpuid stub. For now I just fixed the
>> ICache::line_size and added verification code into vm_version_x86.
>> After 7059226 is fixed I will revisit this Icache code.
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