8133352: aarch64: generates constrained unpredictable instructions
edward.nevill at gmail.com
Tue Aug 11 15:57:33 UTC 2015
fixes an issue reported by one of our partners where aarch64 jdk9 is still generating constrained unpredictable instructions.
The two cases being generates are
STXR Rs, Rt, [Rn] where Rs == Rt
LDAXP Rt1, Rt2, [Rn] where Rt1 == Rt2 (this case is only generated in the assembler smoke test and is not generated in real code)
On the particular vendors HW the behavior for these instructions is to generate a SIGILL.
Unfortunately the fix for this is non trivial, the reason being that
STXR Rs, Rt, [Rn]
requires Rs != Rt != Rn however we only have 2 scratch registers.
The solution I have adopted is to add an addition temp arg to the routines in macroAssembler and pass down an additional temp from the top level usage, but this involves a non trivial amount of code changes.
The alternative solution would be create a temp by pushing a register on the stack.
I am in the process of testing this but I want to get peoples feedback as to whether this is the right solution or whether there is some better way of doing it.
Thanks for your help,
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