RFR: aarch64: 8133842: C2 generates illegal instructions with int shifts >=32

Edward Nevill edward.nevill at gmail.com
Thu Aug 20 10:47:44 UTC 2015


The following webrev


fixes a problem reported by one of our partners whereby C2 can generate illegal instructions on certain partners HW.

JIRA issue here


The problem occurs when you have a logical or arithmetic instruction with a RHS which is shifted by a constant where (const & 32) != 0, ie the constant is 32..63 or 96..127 etc.

For example the following

  res = i | (j >> 53)

generates the instruction

  orrw Rd, Rn, Rm, ASR #53

This instruction has a 6 bit field for the shift so this would appear to be a legal encoding. However certain partner HW treats this as an undefined instruction generating a SIGILL.

The problem was that the rules in aarch64.ad were always anding the constant with 0x3f for both ints and longs.

The above webrev fixes this to mask with 0x1f for ints and 0x3f for longs.

Tested with hotspot and langtools. Results the same in both cases.

Hotspot: Test results: passed: 863; failed: 2; error: 10
Langtools: Test results: passed: 3,263

Thanks for your help with this review,

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