RFR: aarch64: 8133842: C2 generates illegal instructions with int shifts >=32

Edward Nevill edward.nevill at gmail.com
Thu Aug 20 16:06:22 UTC 2015

On Thu, 2015-08-20 at 08:55 -0700, Vladimir Kozlov wrote:
> Changes are fine but I am curious why results will be the same even if you mask less bits - I don't see predicates which 
> checks shift's value (to select different instructions for different shift values) and you use general immI operand type 
> for it.

Not sure I understand the question.

Currently it generate

    orrw Rd, Rn, Rm, ASR #53

Rd, Rn and Rm are 32 bit here (for orrw as opposed to orr).

So on our partners implementation this generates a SIGILL.

The webrev change this to

    orrw Rd, Rn, Rm, ASR #21

which is correct (for Java).

All the best,

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