RFR (S) 8080012: JVM times out with vdbench on SPARC M7-16
vladimir.kozlov at oracle.com
Thu Jul 2 21:34:55 UTC 2015
The author is Igor Veresov.
On big SPARC machines (>1k cores) request for cacheline in PICL takes a
lot of time since we asking it for each core. PICL daemon can't handle
such stream of requests especially when several JVMs start at the same
time (vdbench test).
We were told that on sun4v machines (SPARC-T and -M series) you can't
have different chips with different cache line size. So we can ask only
I reviewed the fix.
The fix was tested on machine which showed the problem.
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