RFR: aarch64: add support for vectorizing floating-point fabs & fneg
felix.yang at linaro.org
Fri Sep 25 04:55:56 UTC 2015
As the patch is not trivial, I also managed to put it on a http server
for your convenience.
Please review this:
Thanks for your help.
On 24 September 2015 at 21:22, Felix Yang <felix.yang at linaro.org> wrote:
> I would like to contribute support for vectorizing fabs & fneg
> instructions on aarch64 architecture.
> The patch takes a similar way as adding support for vectorizing double
> precision sqrt on Intel architectures. And two new tests are added.
> The performance gain for the "sumReductionImplement" function is: 30%
> for single precision and 10% for double precision with LoopMaxUnroll=16.
> I have tested this with JTreg hotspot+langtools+jdk with no
> regressions. Is it OK?
> As this patch involves changes to shared code, I also need an Oracle
> sponsor for it if approved.
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