RFR(S): 8087341: C2 doesn't optimize redundant memory operations with G1
adinn at redhat.com
Fri Feb 12 10:42:15 UTC 2016
A patch for the AArch64 C2 volatile/CAS generation code which deals with
the effects of your proposed C2 patch is available as a webrev
The webrev includes your patch and mine and is based on the latest hs-comp.
n.b. I have /not/ created a separate issue for the AArch64 part of this
fix. I am not sure whether you want to combine it with your patch or
push it as a separate stage.
n.b. your patch allowed the AArch64 C2 code to be significantly
simplified. That's because it ensures that the Raw memory flows
associated with the GC card marks no longer intermingle with the
AliasIdxBot and oop flows associated with the volatile store/CAS. This
means the job of recognising the signature memory configuration between
leading and trailing memory barriers is much easier.
I have verified that this generates correct code for volatile put and
CAS on AArch64 in all 5 relevant GC configurations:
A review from an AArch64 reviewer would be welcome.
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