RFR: 8157841: aarch64: prefetch ignores cache line size

Edward Nevill edward.nevill at gmail.com
Wed May 25 13:41:16 UTC 2016


Please review the following webrev


The aarch64 implementation ignores the actual dcache line size and sets the various prefetch variables based on an assumed cache line size of 64.

One of our partners has a cache line size of 128.

The above patch reads the cache line size from the ctr_el0 register and sets the prefetch variables based on multiples of that instead.


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