RFR: 8199138: Add RISC-V support to Zero

Edward Nevill edward.nevill at gmail.com
Tue Mar 27 08:23:59 UTC 2018


On Tue, 2018-03-27 at 14:10 +0900, John Paul Adrian Glaubitz wrote:
> On 03/24/2018 02:26 AM, Magnus Ihse Bursie wrote:
> > 
> > On 2018-03-20 14:54, Edward Nevill wrote:
> > > Thanks for this. I have updated the webrev with the above comment.
> > > 
> > > http://cr.openjdk.java.net/~enevill/8199138/webrev.01
> > 
> > I note that in platform.m4 (sorry I didn't say this earlier), you set the CPU_ARCH to riscv64 as well, and not just riscv. Now I don't know how likely it is
> > that OpenJDK will ever support the 32-bit version of riscv, but it seems like it would make more sense to define the CPU_ARCH as "riscv", and the CPU as "riscv64".
> > 
> > It's just a minor thing, if you like it the way it is, keep it.
> I agree, this is a bit odd.
> @Edward: Is this correct as it currently is? Would be great if this changeset
> could finally get merged as Debian just recently bootstrapped riscv64 and
> is now building packages on real hardware with 10 build machines running:

Sorry for the delay. I was doing another test build on qemu which takes about 3 days.

Please review the following webrev


This has the following additional changes over the previous webrev

1) Add comment in os_linux.cpp

@@ -1733,6 +1733,9 @@
 #ifndef EM_AARCH64
   #define EM_AARCH64    183               /* ARM AARCH64 */
+#ifndef EM_RISCV                          /* RISCV */
+  #define EM_RISCV      243

   static const arch_t arch_array[]={
     {EM_386,         EM_386,     ELFCLASS32, ELFDATA2LSB, (char*)"IA 32"},

2) Add RISCV to the #error list in os_linux.cpp

@@ -1794,7 +1800,7 @@
   static  Elf32_Half running_arch_code=EM_SH;
     #error Method os::dll_load requires that one of following is defined:\
-        AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, S390, SH, __sparc
+        AARCH64, ALPHA, ARM, AMD64, IA32, IA64, M68K, MIPS, MIPSEL, PARISC, __powerpc__, __powerpc64__, S390, SH, __sparc, RISCV

   // Identify compatability class for VM's architecture and library's architecture

3) Use 'riscv' instead of 'riscv64' for VAR_CPU_ARCH in platform.m4

@@ -114,6 +114,12 @@
+    riscv64)
+      VAR_CPU=riscv64
+      VAR_CPU_ARCH=riscv
+      VAR_CPU_BITS=64
+      VAR_CPU_ENDIAN=little
+      ;;

4) Add riscv to the list of arch which do not have -m64 in flags.m4

@@ -237,7 +237,8 @@
   elif test "x$TOOLCHAIN_TYPE" != xmicrosoft; then
     if test "x$OPENJDK_TARGET_CPU" != xaarch64 &&
-        test "x$OPENJDK_TARGET_CPU" != xarm; then
+        test "x$OPENJDK_TARGET_CPU" != xarm &&
+        test "x$OPENJDK_TARGET_CPU" != xriscv64; then

(This is necessary to get it building again. The previous webrev was based on a rev which did not have the -m64 problem)

I have run this through submit-hs with no problems and as mentioned have also done a complete rebuild under qemu for riscv.

Thanks for your patience,

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