RFR (S) 8078438: Interpreter should support conditional card marks (UseCondCardMark)

Andrew Dinn adinn at redhat.com
Tue Apr 28 14:02:50 UTC 2015

On 28/04/15 14:28, Mikael Gerdin wrote:
>> Hmm.  We were told otherwise here before.  Does the code which scans
>> the card table use a load barrier after each read of the card?  If not
>> the StoreStore won't have any effect anyway.
> Consider the following sequence of events:
> Mutator:        CMS-preclean:
> # o.x == NULL
> o.x = a           
> card[o >> 9] = 0x0    finds card[o >> 9] == 0x0
>             reads o.x, finds NULL
>             writes card[o >> 9] = 0x1
> #            o.x == a becomes visible
> CMS-remark occurs, o.x is not scanned because card[o >> 9] == 0x1 which
> is not dirty.
> There's no load barrier in the card scanning code that I'm aware of.

So, you are saying that CMS depends on the fact that x86/Sparc provide TSO?

If so then I believe for AArch64 that this means:

On the writing side we need to implement StoreCM using either

  dmb  ish
  strb zr, ...

or, preferably

  strbl zr, ...

On the reading side we need the GC thread to execute an acquiring load
when it reads the card, either

  ldrb ...
  dmb ishld

or, preferably

  ldarb ...

How exactly does the GC code do the load -- using generated code or
using a C library routine?

n.b. I am just completing an update to the AArch64 volatile write rules
which deal with volatile object puts. The latest patch moves form
generating a sequence like this

  dmb	ish
  lsr	x10, x13, #9
  str	w14, [x13,#40]
  strb	wzr, [xmethod,x10,lsl #0]
  dmb	ish

to producing something like this

  add	x10, x13, #0x28
  stlr	w14, [x10]
  lsr	x10, x13, #9
  strb	wzr, [x11,x10,lsl #0]

The strb here is the current translation of the StoreCM.

>From what you are saying it appears that we need to implement these
sequences as either:

  dmb	ish
  lsr	x10, x13, #9
  str	w14, [x13,#40]
  dmb ish
  strb	wzr, [xmethod,x10,lsl #0]
  dmb	ish

or, preferably

  add	x10, x13, #0x28
  stlr	w14, [x10]
  lsr	x10, x13, #9
  stlrb	wzr, [x11,x10,lsl #0]

The former will happen automatically if we update the rule for StoreCM
to insert a dmb. The latter can be achieved by providing an alternative
which relies on strlb.

> I think the concept of relaxed memory ordering  archs and CMS is still
> fairly new territory for most people on hotspot-gc-dev, we've been
> living safely in TSO land for a while.

Well, Toto, we are not in Kansas any more :-)


Andrew Dinn

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