CR for RFR 63
Berg, Michael C
michael.c.berg at intel.com
Tue May 17 23:09:45 UTC 2016
I have added components that now handle front to back all assembler emit through a single channel, namely the AMD64Assembler object. All sub classes that extend AMD64RROp and emit SSE code now channel directly through AMD64Assembler object via formal encoding methods. These methods are currently up-propagate-able to AVX based on CPUID check generically for all SIMD emitted code. In this set is the ArrayEquals intrinsic which now has support for AVX with 256bit forms allowed and used there. Please review and comment.
This code was tested as follows (see jbs entry below): mx unittest (no new failures), SpecJvm2008 (all suites pass : I run compress through xml.transform). The code is also checkstyle compliant.
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