Request for reviews (M): 7079329: Adjust allocation prefetching for T4

Vladimir Kozlov vladimir.kozlov at
Tue Aug 16 08:20:09 PDT 2011

I will think about it.


On 8/16/11 6:11 AM, Paul Hohensee wrote:
> Also, is there a way to avoid using #ifdef SPARC in threadLocalAllocBuffer.hpp?
> Maybe add a predicate to vm_version that says whether or not to play the tlab
> reserve game.
> Paul
> On 8/16/11 9:01 AM, Paul Hohensee wrote:
>> You're changing the meaning of an existing flag, AllocatePrefetchLines, to
>> apply only to arrays, right?
>> If so, I'd add another flag for arrays, maybe call it AllocateArrayPrefetchLines,
>> and change the code so AllocatePrefetchLines becomes an optional parameter.
>> E.g., default it to -1 in globals.hpp, and if it's specified on the command line,
>> set both AllocateArrayPrefetchLines and AllocateInstPrefetchLines to the
>> command line value. That would retain backward compatibility: I remember
>> seeing AllocatePrefetchLines used in a few jbb submissions.
>> Also, I'd rename AllocateInstPrefetchLines to AllocateInstancePrefetchLines. 'Inst"
>> is a bit confusing to me and perhaps to others: the first thing I think of is 'instruction'.
>> Paul
>> On 8/15/11 9:12 PM, Vladimir Kozlov wrote:
>>> 7079329: Adjust allocation prefetching for T4
>>> L2 cache line size is 32 bytes on T4 instead of 64 bytes on T series before. As result BIS instruction prefetches
>>> only 32 bytes. Jbb2005 runs show that prefetching 64 bytes is still better on T4 so 2 BIS instructions should be issued.
>>> BIS can't be use for general prefetching since it may fault. New PrefetchAllocation node was added for allocation
>>> prefetching.
>>> Changed prefetchAlloc_bis parameter from memory to regP.
>>> Use AllocatePrefetchInstr on Sparc to allow specify what instruction to use for allocation prefetching (0: prefetch
>>> write, 1: BIS).
>>> Added new instructions on Sparc cacheLineAdrX to reduce number of instructions generated for finding next cache line
>>> address.
>>> Added new flag AllocateInstPrefetchLines to specify number of lines to prefetch for instance allocation.
>>> L1_data_cache_line_size() renamed to prefetch_data_size().

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