Request for reviews (S): 6990015: Incorrect Icache line size is used for 64 bit x86
paul.hohensee at oracle.com
Tue Jun 28 11:04:20 PDT 2011
Your comment in the CR is correct: 32 bytes is used because that's the L1
icache line size on early AMD chips, including, if I recall correctly (and I
might be wrong), Opterons. So we might trigger the guarantee in some
obscure cases, but it'll be obvious what the problem is.
You might want to change the second guarantee to*
guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size * 8 ==
ICache::line_size, "clflush size is not supported");*
On 6/28/11 1:49 PM, Vladimir Kozlov wrote:
> This is for 7u2.
> Fixed 6990015: Incorrect Icache line size is used for 64 bit x86
> Until 7059226 is fixed we can't use information from cpuid to
> determine the cache flashing size since flush_icache stub have to be
> generated before cpuid stub. For now I just fixed the
> ICache::line_size and added verification code into vm_version_x86.
> After 7059226 is fixed I will revisit this Icache code.
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