RFR (M) CR 8050147: StoreLoad barrier interferes with stack usages
john.r.rose at oracle.com
Thu Aug 7 21:28:38 UTC 2014
On Jul 23, 2014, at 11:38 AM, Aleksey Shipilev <aleksey.shipilev at oracle.com> wrote:
> It seems odd this affects Haswell so much. I've checked on my
> SandyBridge laptop, and we have the same code, but performance is
> consistent. Barring that, it would seem like some the second-order
> microarchitectural effect on Haswell. ...which makes me say this is the
> mode we should switch to:
>> ...or "lock addl (%esp-CL-8), 0), pessimistically padding away from
>> stack users:
It's plausible, safe, clean, well-documented, and helps with real chips.
What's not to like?
You can count me as a reviewer.
Nit: sp+C made me itchy, even though it is clarified several sentences down that C<0. Might as well lead off with sp-C.
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