8138894: C1: Support IRIW on weak memory platforms
martin.doerr at sap.com
Thu Oct 8 21:44:15 UTC 2015
Some time ago, we implemented support for ordering of "Independent Reads of Independent Writes" in the template interpreter and C2 Compiler for PPC64. However, it needs to be consistent with C1.
Without "IRIW" support, we generate load-acquire for volatile loads and release-store-fence for volatile stores.
With "IRIW" support, we generate fence-load-acquire for volatile loads and release-store for volatile stores.
CPU_NOT_MULTIPLE_COPY_ATOMIC is currently only defined on PPC64 (though it may be interesting for aarch64 as well).
This change is a prerequisite for our C1 on PPC64 contribution.
Webrev is here:
Please review this change. I need a sponsor, please.
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