RFR(M) 8138894: C1: Support IRIW on weak memory platforms

Doerr, Martin martin.doerr at sap.com
Tue Oct 20 09:02:10 UTC 2015

Hi Christian,

can I consider this change reviewed?
You had a look at it in your reply to my email announcing the C1 PPC64 port. Your reply:


From: Doerr, Martin
Sent: Donnerstag, 8. Oktober 2015 23:47
To: 'hotspot compiler'
Subject: RFR(M) 8138894: C1: Support IRIW on weak memory platforms


Some time ago, we implemented support for ordering of "Independent Reads of Independent Writes" in the template interpreter and C2 Compiler for PPC64. However, it needs to be consistent with C1.

Without "IRIW" support, we generate load-acquire for volatile loads and release-store-fence for volatile stores.

With "IRIW" support, we generate fence-load-acquire for volatile loads and release-store for volatile stores.

CPU_NOT_MULTIPLE_COPY_ATOMIC is currently only defined on PPC64 (though it may be interesting for aarch64 as well).

This change is a prerequisite for our C1 on PPC64 contribution.

Webrev is here:


Please review this change.  I need a sponsor, please.

Best regards,

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