CR for RFR 8154896
Berg, Michael C
michael.c.berg at intel.com
Sun Apr 24 02:14:14 UTC 2016
I would like to contribute a bug fix for SKX/EVEX code gen. There is a guarantee of isBit(imm8) for jccb which can sometimes fail when upper bank register marshaling is required for instructions without EVEX or conditionally EVEX support on SKX. This patch address the minimal set of changes which can have this issue.
This code was tested as follows (see jbs entry below):
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