RFR(M): 8154826: AArch64: take better advantage of base + shifted offset addressing mode
rwestrel at redhat.com
Mon Apr 25 13:43:03 UTC 2016
Thanks for looking at this.
> Hi Roland. This sounds like it has a lot of overlap with JDK-6217251.
> If so, could you update JDK-6217251 explaining what more, if anything,
> needs to be done?
It's similar indeed except that 6217251 suggests using knowledge of the
loop structures to trigger the optimization. My change assumes it's much
more common that the index of an array access is loop variant and the
array itself is not so while it could lead to suboptimal code, it's
> On 4/21/2016 1:23 AM, Roland Westrelin wrote:
>> The aarch64 port implicitly transforms:
>> (AddP base (AddP base address (LShiftL index con)) offset)
>> (AddP base (AddP base offset) (LShiftL index con))
>> in the ad file to embed the shift (and possibly and i2l conversion) into
>> the addressing mode of a memory operation. Exposing that transformation
>> in the ideal graph allows:
>> - (AddP base offset) to be scheduled (for instance outside a loop)
>> - multiple identical (AddP base offset) to be commoned
>> - (LShiftL index con) to be cloned during matching so that each memory
>> access has its own
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