RFR(M): 8154826: AArch64: take better advantage of base + shifted offset addressing mode

Roland Westrelin rwestrel at redhat.com
Mon Apr 25 13:50:53 UTC 2016

On 04/21/2016 10:23 AM, Roland Westrelin wrote:
> http://cr.openjdk.java.net/~roland/8154826/webrev.00/
> The aarch64 port implicitly transforms:
> (AddP base (AddP base address (LShiftL index con)) offset)
> into:
> (AddP base (AddP base offset) (LShiftL index con))
> in the ad file to embed the shift (and possibly and i2l conversion) into
> the addressing mode of a memory operation. Exposing that transformation
> in the ideal graph allows:
> - (AddP base offset) to be scheduled (for instance outside a loop)
> - multiple identical (AddP base offset) to be commoned
> - (LShiftL index con) to be cloned during matching so that each memory
> access has its own

Further testing revealed some problems with the previous change so here
is a new webrev:


Memory access instructions only accept a shift that matches the size of
the data being accessed (i.e. 2 for a 4 byte load). It's not always the
case that address expressions produced by c2 follow that constraint. As
expected, tt's very rare that it doesn't and seem to occur only with
unsafe. I added a predicate that skips the transformation of the address
subtree at the end of the optimization passes and prevent matching of
the address subtree if the constraint is not met for one use. As this is
uncommon, that seems good enough.


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