CR for RFR 8154896
christian.thalinger at oracle.com
Tue Apr 26 19:27:06 UTC 2016
> On Apr 26, 2016, at 8:15 AM, Berg, Michael C <michael.c.berg at intel.com> wrote:
> No, the actual bug fix is in the jccb to jcc changes.
> The assembler change is a correction for compressed displacement.
A “correction”? :-) Anyway, looks good.
> From: Christian Thalinger [mailto:christian.thalinger at oracle.com]
> Sent: Tuesday, April 26, 2016 10:11 AM
> To: Berg, Michael C <michael.c.berg at intel.com>
> Cc: hotspot-compiler-dev at openjdk.java.net
> Subject: Re: CR for RFR 8154896
> On Apr 23, 2016, at 4:14 PM, Berg, Michael C <michael.c.berg at intel.com <mailto:michael.c.berg at intel.com>> wrote:
> <>Hi Folks,
> I would like to contribute a bug fix for SKX/EVEX code gen.
> The bug fix is the change in src/cpu/x86/vm/assembler_x86.cpp, correct?
> There is a guarantee of isBit(imm8) for jccb which can sometimes fail when upper bank register marshaling is required for instructions without EVEX or conditionally EVEX support on SKX. This patch address the minimal set of changes which can have this issue.
> This code was tested as follows (see jbs entry below):
> Bug-id: https://bugs.openjdk.java.net/browse/JDK-8154896 <https://bugs.openjdk.java.net/browse/JDK-8154896>
> http://cr.openjdk.java.net/~mcberg/8154896/webrev.01/ <http://cr.openjdk.java.net/~mcberg/8154896/webrev.01/>
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