RFR(M): 8154826: AArch64: take better advantage of base + shifted offset addressing mode

Andrew Haley aph at redhat.com
Wed Apr 27 15:37:44 UTC 2016


On 04/27/2016 04:32 PM, Vladimir Kozlov wrote:

> Does size of immediate value have affect on latency on aarch64?
> For ConP it is 64-bit constant and for ConN it is 32-bit.

Immediate values are always 16 bits.  To load more than 16 bits you
have to use multiple instructions.  An AArch64 address is 48 bits
wide, so we need three 1-cycle instructions.

> Also, as Martin pointed, such constants are loaded from constant
> table now on SPARC and PPC. What about aarch64?

No, never.  It's too slow: 5 cycles latency, more if you miss L1


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