RFR: 8151340: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
felix.yang at linaro.org
Sat Mar 5 15:54:43 UTC 2016
Please review the following webrev:
As discussed in LKML:
the cost of changing a cache line
from shared to exclusive state can be significant on aarch64 cores,
especially when this is triggered by an exclusive store, since it may
result in having to retry the transaction.
This patch makes use of the "prfm" instruction to prefetch cache lines
for write prior to ldxr/stxr loops. Is it OK?
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