[aarch64-port-dev ] RFR: JDK-8169177 Aarch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
Derek.White at cavium.com
Thu Nov 10 22:14:49 UTC 2016
That's a great find!
My major comment is that the tlab zeroing code should use the macro MacroAssembler::zero_words() already in macroAssembler_aarch64.cpp. zero_words has code to quickly handle zeroing large blocks (using DC ZVA if enabled), and TLABS are relatively large (at least 2KB).
I have an additional question (for the world) if we really need MacroAssembler::zero_memory(), but that can be set aside for a later fix if needed.
- What happened to the assertions in C1_MacroAssembler::initialize_body()?
- Keep MacroAssembler::zero_memory() here.
- Think about calling zero_words instead.
- Don't remove decl of zero_memory() (unless you decide to change all callers to use zero_words instead).
- In MacroAssembler::tlab_refill(), call zero_words() instead of zero_memory().
-zero_words has optimized cases for large zeroing.
- Don't move zero_memory here.
- Don't add decl for zero_memory().
From: aarch64-port-dev [mailto:aarch64-port-dev-bounces at openjdk.java.net] On Behalf Of Kavitha Natarajan
Sent: Thursday, November 10, 2016 6:30 AM
To: aarch64-port-dev at openjdk.java.net; hotspot-compiler-dev at openjdk.java.net
Subject: [aarch64-port-dev ] RFR: JDK-8169177 Aarch64: SIGSEGV when "-XX:+ZeroTLAB" is specified along with GC options
The following are the jtreg test cases that fail with SIGSEGV on aarch64 when "-XX:+ZeroTLAB" is specified along with GC options:
Bug fix for JDK-8086053
<https://bugs.openjdk.java.net/browse/JDK-8086053> (Address inconsistencies regarding ZeroTLAB) fixes similar issue on x86 and sparc.
This is now ported to aarch64 and the above test cases now pass on aarch64 as well.
Below is the webrev for the changes:
Can someone please review ?
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