RFR(M): 8176506: C2: loop unswitching and unsafe accesses cause crash
vladimir.kozlov at oracle.com
Fri May 5 18:07:12 UTC 2017
NativeIllegalInstruction from nativeInst_<arch>.hpp
x86: 0x0B0F, // Real byte order is: 0x0F, 0x0B
But I CCing to Intel for verification. Vivek, is it still true that
these 2 bytes sequence will cause SIGILL? Or you have other sequence?
X86 Manual says:
"Use the 0F0B opcode (UD2 instruction) or the 0FB9H opcode when
deliberately trying to generate an invalid opcode exception (#UD)."
On 5/5/17 7:17 AM, Roland Westrelin wrote:
>> Can use SIGILL (illegal instruction) on all platforms? It should be
>> correctly processed on all platforms and generate hs_err file.
> Ok. Do you have a instruction sequence to recommend to trigger SIGILL on
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