[aarch64-port-dev ] RFR(S): 8214922: Add vectorization support for fmin/fmax

Roland Westrelin rwestrel at redhat.com
Fri Dec 21 15:57:18 UTC 2018

> Yes. Worse than that, it's a piece of AArch64-microarchitecture-specific
> logic in shared code. So it doesn't even apply to all AArch64 implementations.

bool ReductionNode::implemented(int opc, uint vlen, BasicType bt) {
  if (is_java_primitive(bt) &&
      (vlen > 1) && is_power_of_2(vlen) &&
      Matcher::vector_size_supported(bt, vlen)) {
    int vopc = ReductionNode::opcode(opc, bt);
    return vopc != opc && Matcher::match_rule_supported(vopc);
  return false;

Could this be done in Matcher::vector_size_supported() with some changes
to the signature of that method?


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