[aarch64-port-dev ] RFR(S): 8194256 - AARCH64: SIMD shift instructions are incorrectly encoded
ningsheng.jian at linaro.org
Thu Jan 18 01:45:45 UTC 2018
I have created a patch to fix it.
On 17 January 2018 at 18:08, Andrew Haley <aph at redhat.com> wrote:
> On 17/01/18 03:21, Ningsheng Jian wrote:
>> I agree that your patch looks better than original logic. But I found
>> that these instructions are being used in codegen. We need to update
>> the codegen part with your new logic.
>> Some jtreg vect cases failed with your patch:
>> I have created a new bug:
> Ouch. This is bad. I guess you don't know which were affected?
> Andrew Haley
> Java Platform Lead Engineer
> Red Hat UK Ltd. <https://www.redhat.com>
> EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671
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