RFR(M): 8195776: [x86,sparc] A row of minor fixes and enhancements.

Lindenmaier, Goetz goetz.lindenmaier at sap.com
Fri Jan 19 16:31:22 UTC 2018


I would like to contribute a row of smaller fixes to these two platforms.
These are fixes that were done by us inhouse in the past years.

Please review. I please need a sponsor.

Some details:

Move null check info before load LIR_Assembler::emit_alloc_obj. Doesn't make sense after it where it was followed by a non-storage access instruction.

c1 on x86: fix for assertion hit when running with -XX:-ImplicitDiv0Checks
Symptom1: assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
Symptom2: DivByZeroStub was emitted twice per idiv/irem
Fix1: create the lir_idiv without debug info (CodeEmitInfo*). When running with -XX:-ImplicitDiv0Checks the actual idiv cannot trap or reach a safepoint.
Fix2: don't call add_debug_info_for_div0() in the lir assembler. It adds another DivByZeroStub to the stub list.

Data / destination can be reloaded if not volatile causing assertion to fire.

A small optimization for G1: Only call static_write_ref_array_pre from array copy stubs if G1 marking is active.

Fix datatypes of flags in platform xx_globals_<cpu>.hpp files.

Tests of this change will run tonight on all the platforms we build. (hotspot jtreg, jck and a row of bigger tests).

Best regards,

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