RFR: 8216392: Enable cmovP_mem and cmovP_memU instructions
rkennke at redhat.com
Tue Jan 15 11:16:42 UTC 2019
>> I agree with that. However, note that this is not about using cmov vs.
>> branches. This is about generating a load followed by a cmov on the
>> resulting register vs generating a cmov that also does the load and
>> avoids the register. It's pretty much the same data-dependency-wise,
>> except that it avoids using the extra register and encodes smaller.
> Sure, I get that. But, for the reasons given, CMOV is a rather dusty
> corner of the ISA. Intel themselves recommend not using it unless you
> know that the branch is always unpredictable. They say "Use the SETCC
> and CMOV instructions to eliminate unpredictable conditional branches
> where possible. Do not do this for predictable branches." It really
> couldn't be clearer.
Well yeah, but again, this patch isn't about generating cmov or not, it
only changes that a cmov preceded by a load (mov) is generated as single
instruction rather than two instructions for object loads, pretty much
as it's done for all the other types. However, it's not very important
to me, and probably anybody else, otherwise this wouldn't have been
commented-out. I'd withdraw the patch unless somebody steps up and
really wants it.
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