[aarch64-port-dev ] [PATCH] 8217561 : X86: Add floating-point Math.min/max intrinsics, approval request

Pengfei Li (Arm Technology China) Pengfei.Li at arm.com
Wed Mar 6 02:05:58 UTC 2019

Hi Andrew Dinn,

> What seems very odd to me is the difference between fmaxv and fminv.
> Both Q == 1 encodings (i.e. with sz in {0, 1}) are reserved for fmaxv.
> However, the encoding for fminv accepts both Q == 1 encodings with the
> expected interpretation.

In the latest published version of the ArmARM doc, I don't see such difference between fmaxv and fminv.
I guess what you have seen might be a bug of the previous version docs.

> Yes, I think it would probably be better to leave the assert in place and use
> the encoding implied by the SIMD_Arrangement parameter i.e. T2S ==>
> Q=1,sz=0 and T2D ==> Q=1, sz=1. That way the assert will catch errors in
> debug builds and non-debug builds should be stopped by a SIGILL exception.

Thanks, I will do this and post a new webrev in a new thread then.


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