RFR: JDK-8214527 AArch64: ZGC for Aarch64
adinn at redhat.com
Thu Jun 13 08:03:04 UTC 2019
On 12/06/2019 16:18, Stuart Monteith wrote:
> I've added the spilling of floating pointer registers to load_at in
> zBarrierSetAssembler_aarch64.cpp and I've modified aarch64.ad and
> z_aarch64.ad to spill the vector registers, I think. I'd appreciate it
> if Andrew D wouldn't mind giving it a once over - I my wrongness or
> correctness should be obvious - it's not clear to me whether the whole
> 128 bits is spilled, or whether just 64 would be spilled.
I think what you have is all that is needed.
The spilling is implemented by MachSpillCopyNode::implementation() which
is defined in the AD file. It knows the difference between Vec_D and
Vec_X registers. If you can reproduce a spill reliably then you ought to
be able to break that routine in gdb and see what it is doing.
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