RFR: 8256406: G1 x86 C1/Interpreter post write barrier always uses 32 bit to access variable sized PtrQueue::_index

Aleksey Shipilev shade at openjdk.java.net
Tue Nov 17 17:23:10 UTC 2020


On Tue, 17 Nov 2020 12:54:29 GMT, Thomas Schatzl <tschatzl at openjdk.org> wrote:

> Hi all,
> 
>   can I have reviews for this change that fixes benign issues with the G1 C1/interpreter barriers that on x64 only used the lower 32 bit word of the 64 bit PtrQueue::_index member?
> 
> Testing: tier1, linux-x86 builds
> 
> Thanks,
>   Thomas

It looks basically fine, with a minor nit.

src/hotspot/cpu/x86/gc/g1/g1BarrierSetAssembler_x86.cpp line 322:

> 320:   __ movptr(tmp2, queue_index);
> 321:   __ testptr(tmp2, tmp2);
> 322:   __ jcc(Assembler::equal, runtime);

I know it is the same in x86-speak, but `Assembler::zero` would be more readable to show that we actually test `queue_index == 0`.

src/hotspot/share/gc/shared/ptrQueue.hpp line 181:

> 179:   }
> 180: 
> 181:   static constexpr ByteSize byte_width_of_index() { return in_ByteSize(sizeof(size_t)); }

Do we really have to `constexpr` this for `STATIC_ASSERT`? No objection, just curious.

-------------

Changes requested by shade (Reviewer).

PR: https://git.openjdk.java.net/jdk/pull/1257


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