Question about ccs reservation, CDS and aarch64 specifics

Nick Gasson nick.gasson at
Mon Apr 20 02:55:29 UTC 2020

On 04/18/20 14:26 pm, Thomas Stüfe wrote:
> Just occurred to me that aarch64 also relies on SharedBaseAddress being 4G
> aligned. The default is 32G so it works out. If you modify it with
> -XX:SharedBaseAddress, looks like the setting is ignored when the value is
> not usable.

Yes that's correct, it's treated as a hint on AArch64 since
8234794. Because MacroAssembler::{decode,encode}_klass cannot implement
arbitrary base + (src << shift) without an additional temporary register
that isn't always available when it's called. It seems better to
constrain the possible base addresses than reserve a dedicated
compressed class base register.

All the different compressed class decoding modes should now be covered
by the jtreg tests. So if you have access to an AArch64 machine, running
these should be sufficient to prevent regressions. I'm also happy to
help with testing.


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