[vector] Add implementation note on hardware platform limitations

Viswanathan, Sandhya sandhya.viswanathan at intel.com
Wed May 13 00:15:52 UTC 2020

Hi Paul,

Your description looks fine.

Best Regards,

-----Original Message-----
From: panama-dev <panama-dev-bounces at openjdk.java.net> On Behalf Of Paul Sandoz
Sent: Tuesday, May 12, 2020 11:51 AM
To: panama-dev at openjdk.java.net' <panama-dev at openjdk.java.net>
Subject: [vector] Add implementation note on hardware platform limitations


Please review the following change adding an implementation note on hardware platform limitations:

http://cr.openjdk.java.net/~psandoz/panama/vector-impl-restrictions/webrev/ <http://cr.openjdk.java.net/~psandoz/panama/vector-impl-restrictions/webrev/>

I am not sure I got this quite right, appreciate guidance from Intel and ARM folks.

This change is in response to reviews in preparation for integration into jdk/jdk.


Currently the implementation is optimized to work best on:

	• Intel x64 platforms supporting at least AVX2 up to AVX-512. Masking using mask registers and mask accepting hardware instructions on AVX-512 are not currently supported.

	• ARM AArch64 platforms supporting NEON. Although the API has been designed to ensure ARM SVE instructions can be supported (vector sizes between 128 to 2048 bits) there is currently no implementation of such instructions and the general masking capability.

The implementation currently supports masked lane-wise operations in a cross-platform manner by composing the unmasked lane-wise operation with blend as in the expression a.blend(a.lanewise(op, b), m), where a and b are vectors, op is the vector operation, and m is the mask.

The implementation does not currently support optimal vectorized instructions for floating point transcendental functions (such as operators SIN and LOG).

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