[sw-dev] Project proposal: RISC-V port

Bruce Hoult bruce at hoult.org
Thu Feb 8 17:20:35 UTC 2018

Having been involved in porting Microsoft's CoreCLR JIT to ARM (for Tizen
4.0) I'd say that's an underestimate, unless OpenJDK is somehow far better

I can't see either one being done without sponsorship by a major

On Thu, Feb 8, 2018 at 7:12 PM, Andrew Haley <aph at redhat.com> wrote:

> On 07/02/18 22:00, Palmer Dabbelt wrote:
> > There appears to be considerable community interest in a RISC-V
> > OpenJDK port, so my hope is that while I don't have time to directly
> > contribute much myself that we'll be able to get something sane up
> > and running.  Interested users can test on QEMU, and we've recently
> > announced a board (and associated beta program that provide free
> > boards to open source developers) so there's some hardware to run on
> > as well.  I'd like to request that the Porters Group sponsors this
> > project with me as the lead.
> It's a multi-engineer-year project.  Two engineers with deep knowledge
> of HotSpot could get a bare-bones port done in a year, one doing the
> assembler, C1, and template interpreter, and the other doing C2.  Both
> would work on the shared runtime.  To get a really performant port done
> would take at least twice that, probably longer.
> Anyone wanting to lead a porting project had better have plenty of
> time and considerable expertise, or it'll go nowhere.  I'll be happy
> to advise, cajole, and generally encourage, but it's going to take
> boots on the ground.
> --
> Andrew Haley
> Java Platform Lead Engineer
> Red Hat UK Ltd. <https://www.redhat.com>
> EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671
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